A problem in the manufacture of silicon integrated circuits is the formation of certain defects, commonly referred to as dislocations. There are various types of dislocations, but in general, all manifestations are some form of distortion of the crystalline lattice. Dislocations have undesired effects on device yield and reliability because they can provide conductive paths that short out electrical signals.
One source of dislocations arises when crystalline silicon is implanted with a high dose implant that creates structural damage in the crystalline silicon, in many cases making the surface region of the silicon amorphous. During subsequent anneal to electrically activate the implanted region, the damaged region undergoes recrystallization. The recrystallization rate depends on crystallographic direction and proceeds fastest for the (110) and (001) planes. These planes are often aligned along the edges of an implanted region in typical integrated circuit layouts.
As recrystallization proceeds, beginning first at the boundaries between amorphous and recrystallized silicon at the bottom and sides of the implanted region, an area along the intersection of the fast growing (110) and (001) planes undergoes imperfect recrystallization, leaving residual damage in the form of microscopic dislocations. These microscopic dislocations can propagate into longer dislocations, traversing distances on the order of microns, under the application of stress from overlayers or by subsequent processing. Extended dislocations that become electrically active provide a path for undesirable leakage currents that can render a circuit defective.
A prior technique for reducing extended dislocations in germanium implanted regions in a layer of semiconductor material is described in the article "Elimination of end-of-range and mask edge lateral damage in Ge+ preamorphized, B+ implanted Si" by A. C. Ajmera and G. A. Rozgonqi, Appl. Phys. Lett., Vol. 49, No. 19, Nov. 10, 1986, pages 1269-1271. This technique includes forming a layer of oxide over the layer of semiconductor material, photolithographically masking the layer of oxide to define a window region, and performing a wet etch to produce a tapered window in the oxide layer. Subsequent implantation of an impurity through the tapered oxide window produces an implanted region having tapered side edges which result in a reduction in extended dislocations. A drawback to this technique is that it is not compatible with the formation of implanted regions that are self-aligned with gate structures or field oxide regions.